The Nanoscale Communication IC (NCIC) Lab is equipped with state-of-the art millimeter-wave measurement facility. The acquisition of this facility was made possible by a large research grant from the National Science Foundation under contract number: CRI-0551735
 

Ultra Wideband RF IC Design

(Sponsors: NSF, DARPA, Industry)

Ultra Wide-band (UWB) wireless radios are capable of carrying extremely high data rates for up to 250 feet with little transmit power, and high immunity to interference and noise. Furthermore, the spread spectrum characteristics of UWB wireless systems, and the ability of the UWB wireless receivers to resolve the multipath fading due to the nature of the wireless impulse transmission, make UWB systems a promising wireless for a variety of high-rate, short- to medium-range wireless communications. The design of the RF frond-end blocks including frequency synthesizers on both transmitter and receiver sides, and low noise amplifier (LNA)/mixer on the receiver side with bandwidths in excess of 500 MHz is very challenging. Our goal is to explore new design techniques and novel circuit architectures to design the front-end RF circuits including the UWB LNA, mixer, power amplifier, and frequency synthesizer.

An Ultra Wideband (UWB) Two-Stage Distributed CMOS Mixer

Selected publications:

1. Payam Heydari, "A Comprehensive Study of Low-Power Ultra Wideband Radio Transceiver Architectures," IEEE Wireless Communications & Networking Conference (WCNC), March 2005.

2. Amin Q. Safarian, Ahmad Yazdi, Payam Heydari, "Design and Analysis of an Ultra Wide-band Distributed CMOS Mixer,"

4. Payam Heydari and Denis Lin, "A Performance Optimized CMOS Distributed LNA for UWB Receivers," To appear in IEEE Custom Integrated Circuits Conference (CICC), Sept. 2005.

Ultra High-Speed Broadband IC Design

(Sponsors: NSF, Industry)

Various broadband wireline transmission standards have evolved for specific applications, including: (1) Optical Network (SONET) used in wide-area networks for long-haul (50-100km) transmission over fiber and (2) 10-Gigibit Ethernet, used for short- and medium-range communication over optical fiber, as well as short serial back-plane connections over copper. Although these protocols differ in higher-level data processing (e.g., framing), the requirements on the physical layer signal processing are similar for all of them. In particular, the system jitter and noise requirements in these broadband systems pose a number of challenges in the design of the electronic blocks. Operations such as equalization, serialization/deserialization, clock multiplication, and clock recovery are usually done electronically at the desired bit rates – 40Gb/s and higher up to 80Gb/s– require sufficiently accurate timing in the data transitions. Equally important is that the design of front-end high-speed circuits, including the transimpedance amplifier (TIA), laser driver, and channel equalizer, requires a comprehensive knowledge of the channel behavior. In the case of optical transceivers, the research efforts must build a bridge between the optical communications and advanced high-speed IC design.

A Novel Three-Stage Differential Non-Uniform Downsized Distributed Amplifier

Selected publications:

2. Ravindran Mohanavelu and Payam Heydari, "A Novel Flip-Flop-Based Frequency Divider in 0.18mm CMOS," To appear in IEEE European Solid-State Circuits Conference (ESSCIRC), Sept. 2005.

Noise and Signal Integrity in High-Speed Mixed-Signal VLSI Circuits

(Sponsor: NSF)

Noise is a crucial problem in modern mixed-signal VLSI circuits and is becoming increasingly important as the minimum feature size shrinks to 0.13 micron and below. Noise sources are either internal to the devices (e.g., shot noise, 1/f noise, and thermal noise), or external sources (e.g. bounce noise, crosstalk noise, and charge sharing noise). Due to their higher magnitude and energy, the external noise sources play a more important role in determining the circuit reliability and performance.

Power/ground noise, crosstalk, and substrate noise are major external noise sources that can have harmful effects on the circuit performance and reliability. For example, they can cause false switching in the logic gates especially dynamic logic gates, timing failures due to setup and hold time violations, and timing jitter in the on-chip clock generators. The goal of this research is to analysis power/ground noise, crosstalk, and substrate noise in mixed-signal VLSI circuits. We further focus on the effect of power/ground noise and substrate noise on the timing jitter of CMOS phase-locked loops (PLLs) and delay-locked-loops (DLLs).

Selected publications:

1. Payam Heydari, "Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise," IEEE Trans. on Circuits and Systems I, no. 12, vol. 51, pp. 2404-2416, Dec. 2005. (Recipient of IEEE Circuits and Systems Society Darlington Best Paper Award)  

2. Payam Heydari, "Characterizing the Effects of the PLL Jitter Due to Substrate Noise in Discrete-Time Delta-Sigma Modulators," IEEE Trans. on Circuits and Systems I, 2005.