Welcome to Dr. Fadi J. Kurdahi's Website

Links

My Research Interests

  • Early estimation and exploration in hardware/software co-design of embedded systems
  • Design methodology of large scale systems
  • Low-power, process-aware Systems-on-Chip designLow-power, process-aware Systems-on-Chip design
  • Mobile and portable wireless and multimedia systems
  • Reconfigurable computing
  • Software-defined Radio

    • Recent(21st century) Peer-Reviewed Conference Papers

  • Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimizations Proc. IEEE/ACM ISSS'00. pp: 107-113. (with .R. Maestre, M. Fernandez, N. Bagherzadeh, H. Singh).
  • Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures Proceedings of the International Symposium on Field-Programmable Custom Computing Machines, Napa, California, April 2000. pp: 297-298. (with R. Maestre, M. Fernandez, N. Bagherzadeh, H. Singh).
  • Power Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems Proceedings DAC 2001 pp 840-845. (with Liu, J.. Chou, P. and Bagherzadeh, N.).
  • A Data Scheduler for Multi-context reconfigurable architectures Proceedings ISSS2001. pp. 177-182. (with Sanchez-Elez, M. Fernandez, M., Maestre, R., Hermida, R., Bagherzadeh, N.).
  • A constraint-based application model and scheduling techniques for power-aware systems Proc. Of CODES2001. pp 153-158. (with Liu, J. Chou, P., Bagherzadeh, N.).
  • A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture Int. Conf. on Compiler, Architecture and Synthesis for Embedded Systems (CASES 2001), Atlanta, GA, November 2001.(with . Venkataramani, W. Najjar N. Bagherzadeh, W. Bohm).
  • Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 2002. pp: 239-247. (with D. Kulkarni, W. Najjar, R. Rinker)
  • A Novel Systolic VLSI Architecture For Fast RSA Modular Multiplication Proc. AP-AISC2002.August 2002. pp: 81-84. (With Kang, M.).
  • A Case Study of mapping and SDR application onto a reconfigurable DSP core Proc. CODES-ISSS2003. October 2003. pp: 103-108. (With Mohebbi, B, Filho, E., Maestre, R. and Davies, M.)
  • Software-Pipelined 2-D Discrete Wavelet Transform with VLSI Hierarchical Implementation In Proceedings of IEEE International Conference on Robotics, Intelligent Systems and Signal 2003, pages 148-153, Oct. 2003 (with Zheng, C, Long, Y, and Ohm, S.).
  • The coming of age of reconfigurable computing-potentials and challenges of a new technology IEEE Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  ,Volume: 1 , 16-20 Feb. 2004 Pages: xxxii – xxxii (with Najjar, W. ; Vissers, K)
  • On Combining Iteration Space Tiling with Data Space Tiling for Scratch-Pad Memory Systems Proc. 2005 IEEE ASP-DAC. Pp: 18-21. (with Zhang, C.).
  • A High-performance Parallel Mode EBCOT Encoder Architecture Design for JPEG2000 Proc. IEEE-SOCC, Sept. 2004 pp: 213-216. (with Long, Y. and Zheng, C.).
  • System-level SRAM yield Enhancement Proc. IEEE/ISQED 2006, pp 179-184. (with Eltawil, A., Kanj, R., Nassif S. and Park, Y.) (Best paper award. 4 awards out of 290 submissions)
  • System Redundancy: A Means of Improving Process Variation Yield Degradation in Memory Arrays Proc. IEEE/VLSI-DAT. April 2006. (with Eltawil, M.).
  • Reconfigurable computing: is it ready for industry Proc. IEEE ICPS '05 11-14 July 2005 Page(s):337 – 343 (Invited paper)
  • System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis Proc. IEEE/ACM CODES+ISSS 2006. (with S. Pasricha, N. Dutt and Y. Park).
  • Floorplan Driven Leakage power Aware IP-Based SoC Design Space Exploration Proc. IEEE/ACM CODES+ISSS 2006. (with A. Gupta, N. Dutt, K. Khouri and M. Abadir).
  • LEAF: A Leakage-Aware Floorplanner for Systems on Chip Proc. IEEE/ACM ASP-DAC 2007. (with A. Gupta, N. Dutt, K. Khouri and M. Abadir).
  • STEFAL: A System Level Temperature and Floorplan-Aware Leakage Power Estimator for SoCs Proc. IEEE/ACM VLSI 2007. (with A. Gupta, N. Dutt, K. Khouri and M. Abadir).
  • Exploiting Fault Tolerance Towards Power Efficient Wireless Multimedia Applications Proc. IEEE Consumer Communication and Networking Conference (CCNC). Jan. 2007. (with A. A. Djahromi and A. Eltawil)
  • Cross Layer Error Exploitation for Aggressive Voltage Scaling. Proc. IEEE ISQED 2007. March 2007. (with A. A. Djahromi and A. Eltawil).
  • Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design. Proceedings of the 2007 65th IEEE Vehicular Technology Conference VTC2007-Spring. April 2007. (with A. A. Djahromi and A. Eltawil).

    Recent (21st century) Peer-Reviewed Journal Papers

  • Guest Editor's Introduction: Configurable Computing IEEE Design and Test Special Issue on Reconfigurable Computing Volume 17 Issue 1, Jan-March 2000. pp 17-19. (with Baghrezadeh, N. Athanas, P. and Munoz, J.).
  • Morphosys: An Integrated Reconfigurable System for Data-parallel, Computation-Intensive Applications IEEE Trans. on Computers, Vol. 49, No. 5, May 2000. pp: 465 -481. (with H. Singh, M. Lee, G. Lu, N. Bagherzadeg, and E. Filho).
  • Kernel Scheduling Techniques for Efficient Solution Space Exploration in Reconfigurable Computing Journal of Systems Architecture on Modern Methods and Tools in Digital System Design. (with R. Maestre, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh).
  • Automatic Compilation to a Coarse-grained Reconfigurable System-on-Chip (with W. Najjar, G. Venkataramani, W. Bohm and B. Hammes). ACM Trans. Embedded Computer Systems. Volume 2, issue 4 (November 2003). Pp 560-589.
  • A framework for reconfigurable computing: task scheduling and context management IEEE Circuits and Systems Magazine , Volume: 2 Issue: 2 , Second Quarter 2002 ,Page(s): 55 -55. Invited Paper. (with Maestre, R.; Frenandez, M.; Hermida, R.; Bagherzadeh, N.; Singh, H.) VLSI transactions best paper award
  • Guest Editorial: Special Issue on System Synthesis In IEEE Trans. on VLSI (With S. Narayan). Volume 10, Number 4, August 2002.
  • High power keeps cool IEEE Circuits and Devices, Volume: 20 , Issue: 4 ,July-Aug. 2004 Pages:22-30 (with Lucas, M.; Shanbhag, N.; Roy, K.; Fagan, J.;)
  • Compile-time area estimation for LUT-based FPGAs ACM Trans. Design Automation of Electronic Systems, Vol 11, Issue 1 (Jan 2006) pp 104-122. (with D. Kulkarni, W. Najjar, R. Rinker)
  • Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications International Journal of Parallel Programming. Springer. To appear in 2007. (with C. Zhang).

    Recent (21st century) Peer-Reviewed Book Chapters

  • Towards Better Accounting of Physical Design Effects in High Level Synthesis in ``Novel Approaches in Logic and Architecture Synthesis'', A. Mignotte and G. Saucier, Editors, Chapman and Hall 1995. (With C. Ramachandran, P. K. Jha, and N. Dutt).
  • Reconfigurable DSP Platforms In Software-Defined Radio: Baseband for Cellular Technologies, John Wiley & Sons. (With B. Mohebbi). 2004.
  • A Scalable Embedded JPEG2000 Architecture Lecture Notes in Computer Science (Springer-Verlag) Vol 3553/2005. 5th Intl Workshop SAMOS 2005. p 334. 2005. (with C. Zhang and Y. Long)
  • Design and Analysis of Low Power Image Filters toward Defect-Resilient Embedded Memories for Multimedia SoCs 11th Asia-Pacific Computer System Architecture Conference (ACSAC 2006). pp. 295-308. (With Y. Kang, K. Jung, S. Cheng, Y. Park, and A. Eltawil).

    Presentations

  • ASEE presentation 2007

    Mentorship

    Dissertation Committee Chair (* denotes Co-Chair role)

  • James Kim, Full Professor and research director at Sungkyunkwan University, KOREA. Control Synthesis for Pipelined VLSI Architectures. PhD Sept. 1992.
  • D. Sreenivana Rao, Manager, System-level Integration, Analog Devices Inc System-Level Partitioning of VLSI Circuits. Graduated Sept. PhD Spring 1993.
  • Champaka Ramachandran, Synplicity Inc., Sunnyvale, CA. High-Level Synthesis with Accurate Estimation. MS Spring 1990, PhD Jan. 1994.
  • Yu-Lin Chen*, Cadence USA. A Logic Synthesis System Based on Global Dynamic Extraction and Flexible Cost. PhD Spring 1993.
  • Tzongdar Her*, VP of R&D at Siliconware Precision Industries Corp., Taiwan. Transition Activities in Logic Circuits. PhD December 1994.
  • Min Xu, Y Explorations Inc., Lake Forest, CA. Linking high-level synthesis with physical design. PhD Spring 1997.
  • Ming-Hau Lee*, Regional Manager at ARC Corp., Taiwan. Low-power Coarse-grain Architectures. PhD Spring 2000.
  • Hartej Singh*, Senior Design Engineer, Intel Corp, Santa Clara, CA. A Design Methodology for Behavioral-Level Power Exploration. PhD Spring 2000.
  • Guangming Lu*, Senior Engineer, SiRF Corp., Santa Ana, CA. Coarse Grain Reconfigurable Architectures. PhD Spring 2000.
  • Rafael Maestre*, Qualcomm Corp, San Diego, CA. PhD 2000 (UCM/Spain). Kernel Scheduling on the Moprohosys Architecture.
  • Chunhui Zhang, Senior Design Engineer, Intel Corp, Beaverton, OR. PhD 2005 Tiling Exploration and Memory Access Optimization for Embedded Multimedia Systems.

    • Graduate Advisor (Dissertation Committee Chair, in progress, * denotes Co-Chair role)

  • Yun Long. Joined 2001. Passed Qualifying exam (on leave at nVidia Corp.)
  • Young-Hwan Park. Joined 2004. Passed Qualifying Exam.
  • Aseem Gupta*. Joined 2005. Passed Qualifying exam.
  • Stanley Cheng. Joined 2005. Passed Prelim Exam.
  • Mohammad Makhzan. Joined 2005. Passed Prelim Exam.
  • Kiarash Amiri, Joined 2006. Passed Prelim Exam
  • Il-Joon Kim, Joined 2006.

    •   Masters Advisor

  • Erik Jessen, Director, SimpleTech Inc., Irvine, CA. MS Spring 1991. Transformation of Data-Flow Graphs with Conditional Branches into Area-Optimized Netlists.
  • Sharon Yu, Director of ASIC Engineering, Aristos Logic Corp., Rancho Santa Margarita, CA. MS Winter 1992. Automatic Data Flow Schematic Generation.
  • David Lee, Compass Inc., San Jose, CA. MS Spring 1992. Design and Implementation of High-Level Synthesis of Pipelined Data-Path and Clocking Scheme.
  • Sriram Ananthanarayanan, Synopsys Corp. MS Spring 1995. Modeling of ATM switches. (Standard Microsystems Corp. Fellow)
  • Latha Ganesan. MS Spring 1995. Implementation of Register Files.
  • Poonam Agarwal, Synopsys Corp. MS Summer 1996. Power Characterization of Library Components. (Silicon Systems Corp. Fellow).
  • Joseph Balardetta, Director, AMCC Corp. MS Summer 1997. High-Level Synthesis of buffer trees.
  • Farzad Etemadi*, Broadcom Corp and UCI (PhD student). MS Spring 1997. Design and Implementation of a 155.52 Mbps ATM Transceiver
  • Hung-Kang Liu*, Broadcom Corp. MS. Spring 1997. Efficient Structures for Digital Communication Systems.
  • Sadiq Can*. MS Winter 2000. Implementation of compilers for Morphosys.
  • Joseph Saab, Manager, DaimlerChrysler Corp.
  • Mohammad Makhzan. MS summer 2006.

    •   Visiting Postdocs and Scholars Supervised

  • Professor Seong Y. Ohm. Seoul National University. Korea. 1993-1995, 2002-2003.
  • Mr. Antoine Carlier. Institut National Polytechnique de Grenoble. 1995-1996.
  • Professor Dirk Stroobandt. University of Ghent, Belgium. 1997.
  • Dr. Rafael Maestre, Univ. Complutense de Madrid. 1998-2000.
  • Professor Eliseu Chavez Filho. Univ. Federal de Rio de Janeiro, Brazil. 1999-2000.
  • Professor Vladimir Castro Alves. Univ. Federal de Rio de Janeiro, Brazil. 2000.
  • Professor Min-Sup Kang. Anyang University, Korea. 2001-2002.
  • Professor Kang Yi. Handong Global Univ., Korea. 2005-2006.

    • Awards and Honors

  • Phi Beta Delta
  • Graduate Studies Scholarship,
    September 1981 – September 1987
  • ACM SIGDA Awards,
    1984, 1986, 1987, 1990, 1991
  • DAC Distinguished Paper Award,
    June 1986
  • Research Initiation Award,
    July 1989 – June 1992
  • ACM SIGDA Fellowship,
    1991 and 1992
  • Euro-DAC Distinguished Paper Award ,
    September 1992
  • ASP-DAC Distinguished Paper Award,
    January 1997
  • ACM Service Award,
    1999
  • ACM Service Award,
    2000
  • Fulbright Collaborative Research Award,
    2000
  • IEEE VLSI Transactions Best Paper Award,
    January 2002
  • IEEE Senior Member,
    April 2003
  • IEEE Fellow,
    January 2005
  • ISQED Best Paper Award,
    March 2006