Design of VLIW Digital Signal Processor for SDR systems
Studies on new DSP architecture for SDR systems
Studies on signal processing for communications
Design of FFT Processor (Hardware Accelerators)
Development of Assembler, Linker and Simulator of DSP
Cooperate with Synergy Inc. India
Figure 1. SDR Processor Block Diagram.
Figure 2. VLIW Digital Signal Processor Block Diagram.
A very long instruction word (VLIW) digital signal processor (DSP), ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25um 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600MIPS with 100MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, embedded a Viterbi decoder processor and a FFT processor make it possible to implement software defined radio (SDR) applications efficiently.
Figure 3. VLIW Digital Signal Processor Layout.
