SOC SFTWR SYNTHESIS
EECS 222C, Course Code: 18415
Quarter: Fall Quarter 2010
EECS 222C: System-on-Chip Software Synthesis (3)
System-on-Chip software concepts, requirements, examples, for
engineering applications including automotive and communication.
Software synthesis methodology. Algorithmic specification, design
constraints. Applications using embedded operating systems. Static,
dynamic scheduling. Input/output, interrupt handling.
Code generation, retargetable compilation. Instruction set simulation.
Debugging and prototyping.
Prerequisite: EECS 222A or consent of instructor.
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Topic | Reading | |
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1 | Embedded software concepts and requirements | Marwedel: "Embedded System Design", Chapter 1 |
2 | Real-time requirements | Marwedel: "Embedded System Design", Chapter 4a |
3 | Real-time scheduling | Marwedel: "Embedded System Design", Chapter 4b |
4 | SoC software specification | Gerstlauer, Doemer, Peng, Gajski: "System Design: A Practical Guide with SpecC", Chapter 1 |
5 | Embedded software design flow | Gerstlauer, Doemer, Peng, Gajski: "System Design: A Practical Guide with SpecC", Chapter 2 |
6 | Software synthesis | Gerstlauer, Doemer, Peng, Gajski: "System Design: A Practical Guide with SpecC", Chapter 2 |
7 | RTOS targeting and mapping | Marwedel: "Embedded System Design", Chapter 4c |
8 | Target processors | Marwedel: "Embedded System Design", Chapter 3 |
9 | Code generation and compilation | Marwedel, Goossens (editors): "Code Generation for Embedded Processors", Chapters 1-3 |
10 | Instruction-set simulation | Schirner, Sachdeva, Gerstlauer, Doemer: "Modeling, Simulation and Synthesis in an Embedded Software Design Flow...", CECS TR 06-06 |
The Electronic Educational Environment
University of California, Irvine |
http://eee.uci.edu/10f/18415/ |