EMBEDDED SYS MODLNG
EECS 222, Course Code: 17380
Quarter: Winter Quarter 2020
Topic | Posted | Due Date | Comments | |
---|---|---|---|---|
Assignment 1 | Introduction to application example | January 7 | January 15, 6pm | |
Assignment 2 | Introduction to SpecC compiler and simulator | January 14 | January 22, 6pm | |
Assignment 3 | Introduction to SystemC language and simulation | January 21 | January 29, 6pm | |
Assignment 4 | Initial SLDL model of the Canny Edge Decoder | January 28 | February 5, 6pm | |
Assignment 5 | Structural test bench model of the Canny Edge Detector | February 4 | February 12, 6pm | Addendum |
Assignment 6 | Hierarchical DUT model of the Canny Edge Detector | February 11 | February 19, 6pm | A6 and A7 combined |
Assignment 7 | Performance estimation of the Canny Edge Detector | February 11 |
February 19, 6pm |
A6 and A7 combined |
Assignment 8 | Pipelining and parallelization of the Canny Edge Detector | February 18 |
February 26, 6pm |
|
Assignment 9 | Throughput optimization of the DUT pipeline | February 25 |
March 4, 6pm |
The Electronic Educational Environment
University of California, Irvine |
http://newport.eecs.uci.edu/~doemer/w20_eecs222/ |