EMBEDDED SYS MODLNG
EECS 222, Course Code: 18620
Quarter: Winter Quarter 2019


Home | Syllabus | Assignments | Schedule | MessageBoard | Resources

Detailed Class Schedule

(last update: March 14, 2019)

Week Tuesday Thursday
1
January 8
Lecture 1: Introduction and setup
  • Course overview, administration, set up
  • Introduction to embedded system design
  • Levels of abstraction, top-down design flow
January 10
Lecture 2: Embedded system modeling
  • Models of computation
  • System-level description languages
  • Separation of concerns, plug-and-play
2
January 15
Lecture 3: Lecture 3: SpecC system-level description language
  • SpecC language foundation, types
  • Structural and behavioral hierarchy
  • Exception handling
January 17
Lecture 4: SpecC system-level description language
  • Communication and synchronization
  • Timing and timing contraints
  • Library support, persistent annotation
3
January 22
Lecture 5: SpecC system-level description language
  • Communication and synchronization
  • Standard channel library
  • SpecC tools
January 24
Lecture 6: SystemC system-level description language
4
January 29
Lecture 7: SystemC system-level description language
  • SystemC from the ground up (Part 1)
  • Introduction and core concepts
  • SystemC modeling syntax
January 31
Lecture 8: SystemC system-level description language
  • SystemC from the ground up (Part 2)
  • SystemC ports, exports
  • SystemC bus modeling example
5
February 5
Lecture 9: SLDL execution semantics
  • Specification of SLDL semantics
  • Execution and simulation semantics
  • Discrete event simulation algorithm
February 7
Lecture 10: Embedded system specification
  • Test bench structure and communication
  • Structural test bench for application example
  • Control flow for stream processing
6
February 12
Lecture 11: Parallel Discrete Event Simulation
  • Discrete Event Simulation (DES)
  • Parallel Discrete Event Simulation (PDES)
  • Formal execution semantics, time-interval formalism
February 14
Lecture 12: Embedded system specification
  • Specification essentials
  • Specification modeling guidelines
  • Structural refinement of DUT
7
February 19
Lecture 13: Embedded system design exploration
  • Top-down design methodology
  • Specification modeling guidelines
  • System-on-Chip Environment (SCE) demo, part 1
February 21
Lecture 14: Embedded system design exploration
  • Specify-explore-refined design flow
  • Performance profiling and estimation
  • System-on-Chip Environment (SCE) demo, part 2
8
February 26
Lecture 15: Embedded system design flow
  • Top-down refinement-based design flow
  • Architecture and communication refinement
  • System-on-Chip Environment (SCE) demo, part 3
February 28
Lecture 16: Embedded system design flow
  • Performance estimation of the application example
  • Observing simulated time in SystemC, SpecC
  • Pipelining the design-under-test
9
March 5
Lecture 17: Embedded system design flow
  • Modeling of custom hardware components
  • Register Transfer Level (RTL) abstraction
  • RTL modeling in SpecC SLDL
March 7
Lecture 18: Embedded system design flow
  • Throughput optimization of the application example
  • Software optimizations
  • RTL modeling in SystemC SLDL
10
March 12
Lecture 19: Communication abstractions
  • Bus-functional modeling (BFM)
  • Transaction-level modeling (TLM), 1.0 and 2.0
  • SystemC from the ground up (Part 3)
March 14
Lecture 20: Unified Modeling Language (UML)
  • Project review
  • Project discussion
  • Unified Modeling Language (UML) overview
Final
March 21
Final Exam
8:00-10:00am

The Electronic Educational Environment
University of California, Irvine
http://newport.eecs.uci.edu/~doemer/w19_eecs222/